/* $Header: duartchip.h,v 2.2 01/10/02 10:30:19 przybyls Exp $ */


/***********************************************************************/
/* INCLUDE FILE NAME: duarthip.h                                       */
/* ==================                                                  */
/*                                                                     */
/* Author:  Bob Cook                                                   */
/*                                                                     */
/* COMMENT:                                                            */
/*      File contains all SC26C92 specific definitions.                */
/*      See SC26C92 Users Guide for more information.                  */
/*      Also contains ST16C550 specific definitions.                   */
/*                                                                     */
/***********************************************************************/

#ifndef DUARTCHIP_H
#define DUARTCHIP_H

/*****************************/
/*   IFDEFS                  */
/*****************************/


/*****************************/
/*   SYMBOLIC CONSTANTS      */
/*****************************/


/* DEFINES FOR GLOBAL CONFIGURATION CONTROL REGISTER */

#define  SYNC_CYCLE       (BIT8)0x40
#define  ASYNC_CYCLE      (BIT8)0x00
#define  NO_VECTOR        (BIT8)0x00
#define  IVR              (BIT8)0x02
#define  IVR_CHAN         (BIT8)0x04
#define  IVR_TYPE_CHAN    (BIT8)0x06
#define  POWER_DOWN       (BIT8)0x01
#define  DEVICE_ENABLED   (BIT8)0x00


/* DEFINES FOR COMMANDS */

#define  NO_CMD           (BIT8)0x04
/* #define  SET_PTR_MR1      (BIT8)0x10 */
#define  RESET_RX         (BIT8)0x14
#define  RESET_TX         (BIT8)0x1c
#define  RESET_ERROR      (BIT8)0x24
#define  RESET_BREAK_A    (BIT8)0x2c
#define  START_BREAK_A    (BIT8)0x34
#define  STOP_BREAK_A     (BIT8)0x3c
#define  ASSERT_RTS       (BIT8)0x44
#define  NEGATE_RTS       (BIT8)0x4c
#define  ENABLE_TIMEOUT   (BIT8)0x54
/* #define  SET_PTR_MR0      (BIT8)0xB0 */
#define  DISABLE_TIMEOUT  (BIT8)0x64
#define  BLOCK_ERROR_STS  (BIT8)0x6c
#define  XMIT_XON         (BIT8)0x84
#define  XMIT_XOFF        (BIT8)0x8c
#define  GANG_WRITE_XON   (BIT8)0x94
#define  GANG_WRITE_XOFF  (BIT8)0x9c
#define  GANG_LOAD_XON    (BIT8)0xa4
#define  GANG_LOAD_XOFF   (BIT8)0xac
#define  XOFF_RESUME      (BIT8)0xb4
#define  HOST_XOFF        (BIT8)0xbc
#define  CANCEL_XMIT_X    (BIT8)0xc4
#define  RESET_ADD_RECOG  (BIT8)0xdc
#define  RESET_ALL_REG    (BIT8)0xf4
#define  RESET_DEVICE     (BIT8)0xfc


/* DEFINES FOR CONTROL BITS OF THE COMMAND REGISTER */
/* OR TOGETHER PAIRS (ONE RX & ONE TX)              */
/* E.G. ENABLE_RX | DISABLE TX                      */

#define  ENABLE_RX       (BIT8)0x01
#define  DISABLE_RX      (BIT8)0x00
#define  ENABLE_TX       (BIT8)0x02
#define  DISABLE_TX      (BIT8)0x00


/* DEFINES FOR INTERRUPT MASK REGISTER */

#define    INT_TX_RDY       (BIT8)0x01
#define    INT_RX_RDY       (BIT8)0x02
#define    INT_DELTA_BRK    (BIT8)0x04
/* #define    INT_CNTR_RDY     (BIT8)0x08 */
#define    XONOFF_EVENT     (BIT8)0x10
#define    ADD_RECOG_EVENT  (BIT8)0x20
#define    WATCHDOG_TIMEOUT (BIT8)0x40
#define    INT_IN_PORT_CHG  (BIT8)0x80

/* DEFINES FOR INTERRUPT CONTROL REGISTER */

#define    DUART_ENABLE_ALL_INT  (BIT8)0x00
#define    DUART_DISABLE_ALL_INT (BIT8)0x7f

/* DEFINES FOR ACR REGISTER */

/* #define    INT_CTS_CHANGE_A     (BIT8)0x01; */
/* #define    INT_CTS_CHANGE_B     (BIT8)0x02; */




/* DEFINES FOR STATUS REGISTER MASK */

#define    RX_RDY      (BIT8)0x01
#define    RX_FULL     (BIT8)0x02
#define    TX_RDY      (BIT8)0x04
#define    TX_EMT      (BIT8)0x08
#define    OV_RUN_ERR  (BIT8)0x10
#define    PARITY_ERR  (BIT8)0x20
#define    FRAME_ERR   (BIT8)0x40
#define    BRK_RX      (BIT8)0x80



/* DEFINES FOR WATCH DOG TIMER ENABLE REGISTER */

#define    WDTA        (BIT8)0x01
#define    WDTB        (BIT8)0x02
#define    WDTC        (BIT8)0x04
#define    WDTD        (BIT8)0x08


/* baud rate codes to send to CSR register */
#define BR_Code_50       0x00
#define BR_Code_75       0x01
#define BR_Code_150      0x02
#define BR_Code_200      0x03
#define BR_Code_300      0x04
#define BR_Code_450      0x05
#define BR_Code_600      0x06
#define BR_Code_900      0x07
#define BR_Code_1200     0x08
#define BR_Code_1800     0x09
#define BR_Code_2400     0x0a
#define BR_Code_3600     0x0b
#define BR_Code_4800     0x0c
#define BR_Code_7200     0x0d
#define BR_Code_9600     0x0e
#define BR_Code_14400    0x0f
#define BR_Code_19200    0x10
#define BR_Code_28800    0x11
#define BR_Code_38400    0x12
#define BR_Code_57600    0x13
#define BR_Code_115200   0x14
#define BR_Code_230400   0x15

#define UBR_Code_50      0x0900
#define UBR_Code_75      0x0600
#define UBR_Code_150     0x0300
#define UBR_Code_300     0x0180
#define UBR_Code_600     0x00C0
#define UBR_Code_1200    0x0060
#define UBR_Code_2400    0x0030
#define UBR_Code_4800    0x0018
#define UBR_Code_7200    0x0010
#define UBR_Code_9600    0x000C
#define UBR_Code_19200   0x0006
#define UBR_Code_38400   0x0003
#define UBR_Code_57600   0x0002
#define UBR_Code_115200  0x0001


/********************************************/
/*           DUART HOST PORT                */
/********************************************/
/*  FW LABEL        CHIP LABEL      PIN #   */
/*   Tx_A            TxDA            3      */
/*   Rx_A            RxDA            2      */
/*   RTS_A           I/O2A           7      */
/*   DTR_A           I/O3A           4      */
/*   CTS_A           I/O0A           8      */
/*   DSR_A           I/O1A           6      */
/*   DCD_A           GIn1            1      */
/*                   GND             5      */
/*                No Connect         9      */
/********************************************/

/********************************************/
/*           DUART HOST PORT                */
/********************************************/
/*  FW LABEL        CHIP LABEL      PIN #   */
/*   Tx_B            TxDB            3      */
/*   Rx_B            RxDB            2      */
/*   RTS_B           I/O2B           7      */
/*   DTR_B           I/O3B           4      */
/*   CTS_B           I/O0B           8      */
/*   DSR_B           I/O1B           6      */
/*   DCD_B           GIn0            1      */
/*                   GND             5      */
/*                No Connect         9      */
/********************************************/

/********************************************/
/*           DUART SAMPLER PORT             */
/********************************************/
/*  FW LABEL        CHIP LABEL      PIN #   */
/*   Tx_C            TxDC            3      */
/*   Rx_C            RxDC            2      */
/*   RTS_C           I/O2C           7      */
/*   DTR_C           I/O3C           4      */
/*   CTS_C           I/O0C           8      */
/*   DSR_C           I/O1C           6      */
/*   DCD_C           Unused          1      */
/*                   GND             5      */
/*                No Connect         9      */
/********************************************/

/********************************************/
/*           DUART SAMPLER PORT             */
/********************************************/
/*  FW LABEL        CHIP LABEL      PIN #   */
/*   Tx_D            TxDD            3      */
/*   Rx_D            RxDD            2      */
/*   RTS_D           I/O2D           7      */
/*   DTR_D           I/O3D           4      */
/*   CTS_D           I/O0D           8      */
/*   DSR_D           I/O1D           6      */
/*   DCD_D           Unused          1      */
/*                   GND             5      */
/*                No Connect         9      */
/********************************************/

/*******************************************/
/*                                         */
/*              INPUT PORT                 */
/*                                         */
/*    7 6 5 4   3 2 1 0                    */
/*    | | | |   | | | |                    */
/*    | | | |   | | | +-- CTS_A            */
/*    | | | |   | | +---- CTS_B            */
/*    | | | |   | +------ DSR_A            */
/*    | | | |   +-------- DCD_A            */
/*    | | | |                              */
/*    | | | +------------ DSR_B            */
/*    | | +-------------- DCD_B            */
/*    | +---------------- Undefined        */
/*    +------------------ Undefined        */
/*                                         */
/*******************************************/


/*******************************************/
/*                                         */
/*             OUTPUT PORT                 */
/*                                         */
/*    7 6 5 4   3 2 1 0                    */
/*    | | | |   | | | |                    */
/*    | | | |   | | | +-- RTS_A            */
/*    | | | |   | | +---- RTS_B            */
/*    | | | |   | +------ DTR_A            */
/*    | | | |   +-------- DTR_B            */
/*    | | | |                              */
/*    | | | +------------ Unused           */
/*    | +---------------- Unused           */
/*    +------------------ Unused           */
/*                                         */
/*******************************************/

/********************************************/
/*            LOOP BACK CONNECTOR           */
/********************************************/
/*  SIGNAL                 PIN CONNECTION   */
/*   Tx to Rx               3 to 2          */
/*   RTS to CTS             7 to 8          */
/*   DTR to DSR and DCD     1 to 4 and 6    */
/********************************************/

/* MASK FOR MODEM CONTROL LINES */

#define    RTS        (BIT8)0x04
#define    DTR        (BIT8)0x08

#define    CTS        (BIT8)0x01
#define    DSR        (BIT8)0x02

#define    INT_CTS_CHANGE       (BIT8)0x10;

/* #define    RTS_B      (BIT8)0x02 */
/* #define    DTR_B      (BIT8)0x08 */

/* #define    CTS_B      (BIT8)0x02 */
/* #define    DSR_B      (BIT8)0x10 */
/* #define    DCD_B      (BIT8)0x20 */


/*****************************/
/* DEFINES FOR ST16C550 UART */
/*****************************/

/* Define register addresses */

#define    U_RHR        (BIT8)0x00  /* Receive Holding Register */
#define    U_THR        (BIT8)0x00  /* Transmit Holding Register */
#define    U_IER        (BIT8)0x01  /* Interrupt Enable Register */
#define    U_FCR        (BIT8)0x02  /* FIFO Control Register */
#define    U_ISR        (BIT8)0x02  /* Interrupt Status Register */
#define    U_LCR        (BIT8)0x03  /* Line Control Register */
#define    U_MCR        (BIT8)0x04  /* Modem Control Register */
#define    U_LSR        (BIT8)0x05  /* Line Status Register */
#define    U_MSR        (BIT8)0x06  /* Modem Status Register */
#define    U_SPR        (BIT8)0x07  /* Scratchpad Register */
#define    U_DLL        (BIT8)0x00  /* LSB of Divisor Latch */
#define    U_DLM        (BIT8)0x01  /* MSB of Divisor Latch */

/* Define fields in the registers */
#define    U_MSI        (BIT8)0x08  /* IER modem status interrupt */
#define    U_RLSI       (BIT8)0x04  /* IER receive line status interrupt */
#define    U_THRI       (BIT8)0x02  /* IER transmit holding register interrupt */
#define    U_RHRI       (BIT8)0x01  /* IER receive holding register interrupt */
#define    U_RCVRTL1    (BIT8)0x00  /* FCR receive FIFO trigger level = 1 */
#define    U_RCVRTL4    (BIT8)0x40  /* FCR receive FIFO trigger level = 4 */
#define    U_RCVRTL8    (BIT8)0x80  /* FCR receive FIFO trigger level = 8 */
#define    U_RCVRTL14   (BIT8)0xC0  /* FCR receive FIFO trigger level = 14 */
#define    U_DMAMS      (BIT8)0x08  /* FCR DMA mode select */
#define    U_XFR        (BIT8)0x04  /* FCR XMIT FIFO reset */
#define    U_RFR        (BIT8)0x02  /* FCR RCVR FIFO reset */
#define    U_FEN        (BIT8)0x01  /* FCR FIFO enable */
#define    U_INTS       (BIT8)0x01  /* ISR INT status */
#define    U_DLE        (BIT8)0x80  /* LCR divisor latch enable */
#define    U_SETB       (BIT8)0x40  /* LCR set break */
#define    U_NP         (BIT8)0x00  /* LCR no parity */
#define    U_OP         (BIT8)0x08  /* LCR odd parity */
#define    U_EP         (BIT8)0x18  /* LCR even parity */
#define    U_MP         (BIT8)0x28  /* LCR mark parity */
#define    U_SP         (BIT8)0x38  /* LCR space parity */
#define    U_SB         (BIT8)0x04  /* LCR stop bits */
#define    U_WL5        (BIT8)0x00  /* LCR word length = 5 */
#define    U_WL6        (BIT8)0x01  /* LCR word length = 6 */
#define    U_WL7        (BIT8)0x02  /* LCR word length = 7 */
#define    U_WL8        (BIT8)0x03  /* LCR word length = 8 */
#define    U_LBM        (BIT8)0x10  /* MCR loop back mode */
#define    U_OP2        (BIT8)0x08  /* MCR set OP2 */
#define    U_OP1        (BIT8)0x04  /* MCR set OP1 */
#define    U_RTS        (BIT8)0x02  /* MCR force RTS */
#define    U_DTR        (BIT8)0x01  /* MCR force DTR */
#define    U_FDER       (BIT8)0x80  /* LSR FIFO data error */
#define    U_TE         (BIT8)0x40  /* LSR transmit empty */
#define    U_THE        (BIT8)0x20  /* LSR transmit holding empty */
#define    U_BI         (BIT8)0x10  /* LSR break interrupt */
#define    U_FER        (BIT8)0x08  /* LSR framing error */
#define    U_PER        (BIT8)0x04  /* LSR parity error */
#define    U_OER        (BIT8)0x02  /* LSR overrun error */
#define    U_RDR        (BIT8)0x01  /* LSR receive data ready */
#define    U_CD         (BIT8)0x80  /* MSR CD */
#define    U_RI         (BIT8)0x40  /* MSR RI */
#define    U_DSR        (BIT8)0x20  /* MSR DSR */
#define    U_CTS        (BIT8)0x10  /* MSR CTS */
#define    U_DCD        (BIT8)0x08  /* MSR delta CD */
#define    U_DRI        (BIT8)0x04  /* MSR delta DRI */
#define    U_DDSR       (BIT8)0x02  /* MSR delta DSR */
#define    U_DCTS       (BIT8)0x01  /* MSR delta CTS */


/*****************************/
/*   TYPEDEFS                */
/*****************************/

/*****************************/
/*   MACROS                  */
/*****************************/

/*****************************/
/*   FUNCTION PROTOTYPES     */
/*****************************/


#endif
